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- W2008846062 abstract "This paper presents a scaling-friendly continuous-time closed-loop VCO-based ΔΣ ADC. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly OTAs and precision comparators. It arranges two VCOs in a pseudo-differential manner, which cancels out even-order distortions. More importantly, it brings an intrinsic clocked averaging (CLA) capability that automatically addresses DAC mismatches. The prototype ADC in 130nm CMOS occupies a small area of 0.03mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and achieves 66.5dB SNDR over 2MHz BW while sampling at 300MHz and consuming 1.8mW under a 1.2V power supply. It can also operate with a low analog supply of 0.7V and achieves 65.8dB SNDR while consuming 1.1mW. The corresponding figure-of-merits (FOMs) for the two cases are 0.25pJ/step and 0.17pJ/step respectively." @default.
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- W2008846062 date "2013-09-01" @default.
- W2008846062 modified "2023-10-17" @default.
- W2008846062 title "A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA" @default.
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- W2008846062 doi "https://doi.org/10.1109/cicc.2013.6658455" @default.
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