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• W2009503188 abstract "Electronic design Automation (EDA) tools are used for design verification before fabrication of the integrated circuits. The accuracy of the power measured using these EDA Tools are overlooked since the approximations are good enough to take design decisions. An error in the range of 9.6 – 14.18% is observed between the power indicated in the circuit by the tool and theoretical calculations. These approximations are not very well documented by the EDA tool vendors. Of late, with IP based design flow, power has been the major parameter to assess the quality of the IP core and accuracy of the power measurement of the CAD tools is important. The EDA simulation tools come with built-in functions to measure the power consumption. [1] In this paper we present different ways of measuring the power of the circuit using the EDA simulation tools and their accuracy when compared with the theoretical computations. Work demonstrates the most appropriate method of power measurement in a circuit using Cadence Virtuoso Analog design environment and its result browser." @default.
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• W2009503188 date "2012-03-01" @default.
• W2009503188 modified "2023-09-25" @default.
• W2009503188 title "Accurate power measurement methodology for VLSI circuits using CAD tools" @default.
• W2009503188 cites W2145748811 @default.
• W2009503188 doi "https://doi.org/10.1109/icdcsyst.2012.6188642" @default.
• W2009503188 hasPublicationYear "2012" @default.
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