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- W2010290923 abstract "In this paper, a design of JTAG-based configuration circuit applied in 2.5 Gbps SerDes (Serializer & Deserializer) mixed digital-analog chip is implemented with SMIC 0.13um technology. The configuration circuit mainly involves two functional components: CR control port and JTAG interface module. The control signals of the whole chip are incorporated in a group of control registers (CRs), which can be accessed through CR control port. The JTAG architecture with 5 standard pins is adopted to load a stream of override data bits into CR port. By applying this combinational configuration methodology, the amount of pinout of the chip has been largely reduced, thus resulting in an efficient saving of chip area. The testing result shows the configuration circuit works perfectly in actual system." @default.
- W2010290923 created "2016-06-24" @default.
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- W2010290923 date "2011-10-01" @default.
- W2010290923 modified "2023-09-27" @default.
- W2010290923 title "A JTAG-based configuration circuit applied in SerDes chip" @default.
- W2010290923 cites W2028504835 @default.
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- W2010290923 doi "https://doi.org/10.1109/asicon.2011.6157303" @default.
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