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- W2010338509 abstract "A 1V l2b 40MS/s pipelined ADC using a proposed two stage folded cascode opamp for low voltage and a proposed frequency compensation technique for fast settling achieves a FOM of 0.39pJ/conversion-step. The prototype ADC implemented in a 90nm digita1 CMOS process with an active die area of 0.28mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> consumes 16mW from a 1V power supply. It shows 62dB SNDR and 73dB SFDR for a 5 MHz input at a 40MHz samplinlg clock." @default.
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- W2010338509 date "2007-06-01" @default.
- W2010338509 modified "2023-10-16" @default.
- W2010338509 title "A 9Onm CMOS 0.28mm<sup>2</sup> 1V 12b 40MS/s ADC with 0.39pJ/Conversion-Step" @default.
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- W2010338509 doi "https://doi.org/10.1109/vlsic.2007.4342713" @default.
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