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- W2010472198 abstract "Electrical performance and area improvement are important parts of the overall VLSI design task. Given designer specified constraints on area, delay, and power, EPOXY will size a circuit's transistors and will attempt small circuit changes to help meet the constraints. In addition, the system provides a flexible framework within which to evaluate the effects of different area and electrical models, as well as different optimization algorithms. Since the sum of transistor area is a better measure of dynamic power than cell area, a more accurate area model is presented. Optimization of a CMOS eight-stage inverter chain illustrates this difference; a typical minimum power implementation is 32.3% larger than the one for minimum area. The combination of a TILOS-style heuristic and augmented Lagrangian optimization algorithm yields quality results rapidly. EPOXY'S circuit analysis is from 5 to 56 times faster than Crystal." @default.
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- W2010472198 date "1988-06-01" @default.
- W2010472198 modified "2023-09-24" @default.
- W2010472198 title "An electrical optimizer that considers physical layout" @default.
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- W2010472198 doi "https://doi.org/10.5555/285730.285803" @default.
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