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• W2010802738 abstract "This paper considers Rigel, a programmable accelerator architecture for a broad class of data- and task-parallel computation. Rigel comprises 1000+ hierarchically-organized cores that use a fine-grained, dynamically scheduled single-program, multiple-data (SPMD) execution model. Rigel's low-level programming interface adopts a single global address space model where parallel work is expressed in a task-centric, bulk-synchronized manner using minimal hardware support. Compared to existing accelerators, which contain domain-specific hardware, specialized memories, and/or restrictive programming models, Rigel is more flexible and provides a straightforward target for a broader set of applications." @default.
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• W2010802738 date "2009-06-20" @default.
• W2010802738 modified "2023-10-18" @default.
• W2010802738 title "Rigel" @default.
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• W2010802738 doi "https://doi.org/10.1145/1555754.1555774" @default.
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