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- W2010884102 abstract "The HSSP processor for 3-D graphics applications is described. The HSSP chip has a regular structure owing to a skewed systolic array architecture. This novel VLSI-oriented architecture was applied to real-time 3-D graphics image generation, which requires very high processing throughput. The HSSP eliminates hidden portions of surfaces from a viewer, and gives a constant intensity or a smooth shaded intensity to each surface. It uses a scan-line Z-buffer algorithm, and outputs the resulting image in the scan line, pixel by pixel in a serial manner. The chip is fabricated in 1.2- mu m twin-tub CMOS technology. It contains 330 K transistors on a 11.06*11.05-mm die, and operates with a 20-MHz single-phase clock.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2010884102 date "1988-01-01" @default.
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- W2010884102 title "A hidden surface and shading processor (HSSP) with a systolic architecture" @default.
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- W2010884102 doi "https://doi.org/10.1109/4.5950" @default.
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