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- W2011169262 abstract "The CMOS/SOS Microsignal Processor (µSP) is a 12-bit general purpose programmable, pipelined signal processor designed to efficiently perform digital filtering and processing algorithms. The architecture of the µSP is built of three elements - control, arithmetics, and memory: control consists of a sequencer and address generator; arithmetics consist of a scaler/shifter, 12 x 12 multiplier, a dual ALU and multipart memories; and Data memory consists of commercial 4K memory chips. Programmability is achieved through a stored program which calls and implements desired micro instructions in the arithmetic pipeline. A typical µSP can be programmed to implement various length complex or real FFTs, perform correlation/convolution, and sundry vector operations and digital filtering tasks. For example, the three architecture elements - control, memory and arithmetics operate in parallel to per-form a 1024 pt complex FFT in 3 ms (memory to memory). A typical CMOS/SOS µSP is designed for single chip carriers grouped into six hybrid types and fit onto one two-sided 6 in. by 9 in. module. The µSP is designed to be T2L interface compatible and operate at 10 V with 30-35 W of power dissipation. This paper will present the background leading to the design, describe the architecture and discuss the CMOS/SOS chips involved in the design.© (1978) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only." @default.
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- W2011169262 date "1978-12-08" @default.
- W2011169262 modified "2023-09-26" @default.
- W2011169262 title "<title>CMOS/SOS Microsignal Processor</title>" @default.
- W2011169262 doi "https://doi.org/10.1117/12.938250" @default.
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