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- W2011243677 abstract "Electrical stress-relieved analog circuit design techniques using only baseline devices are presented, 1-to-2 logic level shifter, optional diode insertion, and adaptive biasing scheme are introduced to meet a reliability guideline that ensures sufficient lifetime. The proposed idea was successfully demonstrated with 12-bit <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>I/Q</i> digital-to-analog converter (DAC) and an operational amplifier having a Classs-AB output stage in 65-nm n-well CMOS technology and a high temperature operating life (HTOL) test was performed to evaluate the reliability of the design." @default.
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- W2011243677 date "2007-10-01" @default.
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- W2011243677 title "High-Voltage-Tolerant Analog Circuits Design in Deep-Submicrometer CMOS Technologies" @default.
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- W2011243677 doi "https://doi.org/10.1109/tcsi.2007.904600" @default.
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