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- W2011269063 abstract "Based on the power consumption analysis of a real dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3, it appears that the key of power saving is keeping the datapath on the processing element (PE) array as possible. Fine grain partial reconfiguration (FGPR) is a simple technique to minimize the change of configuration code in a hardware context switching. In FGPR, a configuration code is divided into several components and only the configuration data for the required components are changed. Evaluation results demonstrate that about 15% of the power consumption is reduced with only 0.7% hardware overhead. The total amount of configuration data and its loading time can be also reduced by 37% in average." @default.
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- W2011269063 date "2009-08-01" @default.
- W2011269063 modified "2023-09-25" @default.
- W2011269063 title "Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors" @default.
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- W2011269063 doi "https://doi.org/10.1109/fpl.2009.5272435" @default.
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