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- W2011338638 abstract "This paper presents a python based High-Level synthesis (HLS) compiler. The compiler interprets an algorithmic description of a desired behavior written in Python and map it to VHDL. FPGA combines many benefits of both software and ASIC implementations. Like software, the mapped circuit is flexible, and can be reconfigured over the lifetime of the system. FPGAs therefore have the potential to achieve far greater performance than software as a result of bypassing the fetch-decode-execute operations of traditional processors, and possibly exploiting a greater level of parallelism. Creating parallel programs implemented in FPGAs is not trivial. This article describes design, implementation and first results of created Python based compiler." @default.
- W2011338638 created "2016-06-24" @default.
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- W2011338638 date "2014-11-25" @default.
- W2011338638 modified "2023-09-27" @default.
- W2011338638 title "Python based high-level synthesis compiler" @default.
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- W2011338638 doi "https://doi.org/10.1117/12.2075988" @default.
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