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- W2011761036 abstract "A fully-pipelined tile-able 1MB SRAM IP with a 0.127um2 cell in a HKMG 28nm bulk technology has an area of 1.39mm2/MB with 79.2% array efficiency. It operates with 2-cycle latency up to 1GHz. The no-repair hardware has a circuit limited yield of 99.92 and 53% at 100 and 850MHz, respectively with 0.75V VDD. A Data Retention Voltage of 0.42V has been measured." @default.
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- W2011761036 date "2013-09-01" @default.
- W2011761036 modified "2023-09-23" @default.
- W2011761036 title "A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm<sup>2</sup> per MB" @default.
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- W2011761036 doi "https://doi.org/10.1109/cicc.2013.6658452" @default.
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