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- W2011784911 abstract "Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)" @default.
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- W2011784911 date "2006-11-01" @default.
- W2011784911 modified "2023-10-16" @default.
- W2011784911 title "High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4" @default.
- W2011784911 cites W1817239747 @default.
- W2011784911 doi "https://doi.org/10.1109/norchp.2006.329238" @default.
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