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Matches in SemOpenAlex for { <https://semopenalex.org/work/W2012187127> ?p ?o ?g. }

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• W2012187127 abstract "The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a reset state of a circuit is a hard problem. In this paper we propose a method allowing usage of SAT-based verification methods without a need for a user-given or a computed initial state. The idea is to employ a binary encoding of 3-valued modeling of circuits, and use the undefined state X as a reset state." @default.
• W2012187127 created "2016-06-24" @default.
• W2012187127 creator A5025992214 @default.
• W2012187127 creator A5068008369 @default.
• W2012187127 date "2003-01-01" @default.
• W2012187127 modified "2023-09-27" @default.
• W2012187127 title "SAT-Based Methods for Sequential Hardware Equivalence Verification without Synchronization" @default.
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• W2012187127 doi "https://doi.org/10.1016/s1571-0661(05)82545-9" @default.
• W2012187127 hasPublicationYear "2003" @default.
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