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- W2012302282 abstract "A design strategy to optimise the bias currents of low-power cascaded emitter coupled logic (ECL) gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimises the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20 GHz bipolar process are also given." @default.
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- W2012302282 date "2006-01-01" @default.
- W2012302282 modified "2023-09-23" @default.
- W2012302282 title "Design of cascaded ECL gates with power constraint" @default.
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- W2012302282 doi "https://doi.org/10.1049/el:20064002" @default.
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