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- W2012380465 abstract "Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-V T region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0µm/0.6µm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology." @default.
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- W2012380465 date "2011-11-01" @default.
- W2012380465 modified "2023-09-24" @default.
- W2012380465 title "Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS" @default.
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- W2012380465 doi "https://doi.org/10.1109/norchp.2011.6126698" @default.
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