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• W2013217594 abstract "Optimal process integration for array devices of bit-cost scalable (BiCS) flash memory is successfully developed. We adopt SiN-based gate dielectrics for the consistency with the 'gate-first' process which is unique to BiCS flash technology, and 'macaroni' body FETs for better controllability over the sub-threshold characteristics of depletion-mode poly-silicon transistors. With these technologies and newly devised 4F <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> cell array, BiCS flash becomes a promising candidate for future ultra-high density memory." @default.
• W2013217594 created "2016-06-24" @default.
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• W2013217594 date "2007-01-01" @default.
• W2013217594 modified "2023-09-30" @default.
• W2013217594 title "Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory" @default.
• W2013217594 cites W1989184594 @default.
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• W2013217594 doi "https://doi.org/10.1109/iedm.2007.4418970" @default.
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