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- W2013281636 abstract "The Field-Programmable Gate Array is an excellent match for the Sparse Matrix-Vector Multiply (SMVM) operation because of its enormous computational capacity and its ability to build a custom memory hierarchy that matches the memory access patterns of the operation. This paper describes a new sparse matrix storage format which works in conjunction with a custom memory subsystem which decodes the format on-the-fly. The SMVM operation is implemented on a single FPGA and a small parallel system of four FPGAs. The parameters that affect the performance of the sequential and parallel designs are investigated as well as the speedup for different matrices." @default.
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- W2013281636 date "2014-11-01" @default.
- W2013281636 modified "2023-10-14" @default.
- W2013281636 title "A hardware–software co-design approach for implementing sparse matrix vector multiplication on FPGAs" @default.
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- W2013281636 doi "https://doi.org/10.1016/j.micpro.2014.02.004" @default.
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