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• W2013305417 startingPage "54" @default.
• W2013305417 abstract "Design techniques to provide robustness against loop saturation due to blockers in ΣA modulators are presented. Loop overload detection and correction are employed to improve the analog-to-digital converters (ADCs) tolerance to strong blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADCs blocker tolerance, a minimally invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. Measurement results show that the proposed ADC implemented in a 90nm CMOS process achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5 dBFS while the conventional feedforward modulator becomes unstable at -23.5 dBFS of blocker power. The proposed blocker rejection techniques are minimally invasive and take less than 0.3 μs to settle after a strong agile blocker appears." @default.
• W2013305417 created "2016-06-24" @default.
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• W2013305417 date "2015-01-01" @default.
• W2013305417 modified "2023-09-27" @default.
• W2013305417 title "Design Techniques to Improve Blocker Tolerance of Continuous-Time <inline-formula> <tex-math notation=LaTeX>$DeltaSigma$ </tex-math></inline-formula> ADCs" @default.
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• W2013305417 doi "https://doi.org/10.1109/tvlsi.2014.2303815" @default.
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