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• W2014010346 abstract "We have achieved aggressive reduction of V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>T</inf> variation and V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD-min</inf> by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>T</inf> variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD-min</inf> reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout." @default.
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• W2014010346 date "2011-12-01" @default.
• W2014010346 modified "2023-10-17" @default.
• W2014010346 title "Advanced channel engineering achieving aggressive reduction of V<inf>T</inf> variation for ultra-low-power applications" @default.
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• W2014010346 doi "https://doi.org/10.1109/iedm.2011.6131657" @default.
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