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• W2014072102 abstract "This paper presents a low damage inductively coupled plasma (ICP) etching process to define sub-100 nm platinum gate lines for III–V metal–oxide–semiconductor field-effect transistors (MOSFETs) fabrication. In this process, a negative resist etching mask patterned by electron beam lithography is used to define the high resolution platinum features using a combination of SF 6 and C 4 F 8 etch gases. Systematic investigation of the impact of various etch conditions, such as coil and platen power, gas composition, chamber pressure on etch rate and profile, resulted in a controllable etching process. Optical emission spectra of the ICP plasma have been checked for better understanding the etching mechanism. Etch induced damage of the underlying device channel of the III–V MOSFET materials has been evaluated through monitoring the sheet resistance variation of the materials at room temperature, which showed the process does not significantly degrade the electrical properties of the underlying device channel under optimized conditions." @default.
• W2014072102 created "2016-06-24" @default.
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• W2014072102 date "2012-01-01" @default.
• W2014072102 modified "2023-09-25" @default.
• W2014072102 title "A Low Damage Etching Process of Sub-100 nm Platinum Gate Line for III–V Metal–Oxide–Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF₆/C₄F₈" @default.
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• W2014072102 doi "https://doi.org/10.1143/jjap.51.01ab01" @default.
• W2014072102 hasPublicationYear "2012" @default.
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