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• W2014671469 abstract "Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random care bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2–3 times speed up in test write time compared to conventional RAS." @default.
• W2014671469 created "2016-06-24" @default.
• W2014671469 creator A5014114241 @default.
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• W2014671469 date "2010-05-01" @default.
• W2014671469 modified "2023-09-23" @default.
• W2014671469 title "Test application time minimization for RAS using basis optimization of column decoder" @default.
• W2014671469 cites W1506569352 @default.
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• W2014671469 doi "https://doi.org/10.1109/iscas.2010.5537094" @default.
• W2014671469 hasPublicationYear "2010" @default.
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