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- W2014672807 abstract "Abstract Enclosed-layout transistors fabricated in standard CMOS processes are known to offer a natural robustness against radiation effects, a characteristic which is boosted in submicron technologies due to the reduction of the oxide thickness. In this paper, a thorough analytical I–V model of short-channel polygonal enclosed-layout transistors is proposed, addressing the issues of drain-induced barrier lowering and threshold voltage roll-off due to short-channel effects. Experimental data is reported, showing good agreement with the theoretical model." @default.
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- W2014672807 date "2009-05-01" @default.
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- W2014672807 title "Analytical model of short-channel gate enclosed transistors using Green functions" @default.
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- W2014672807 doi "https://doi.org/10.1016/j.sse.2009.01.018" @default.
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