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- W2014748579 abstract "The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm2." @default.
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- W2014748579 date "2013-11-01" @default.
- W2014748579 modified "2023-09-26" @default.
- W2014748579 title "Digital calibration technique using a signed counter for charge pump mismatch in phase‐locked loops" @default.
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- W2014748579 doi "https://doi.org/10.1049/iet-cds.2013.0011" @default.
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