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• W2015184411 abstract "DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage." @default.
• W2015184411 created "2016-06-24" @default.
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• W2015184411 date "2012-02-01" @default.
• W2015184411 modified "2023-10-17" @default.
• W2015184411 title "A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and &#x00D7;4 half-page architecture" @default.
• W2015184411 cites W1964108470 @default.
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• W2015184411 doi "https://doi.org/10.1109/isscc.2012.6176869" @default.
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