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- W2015184974 abstract "This paper describes the design of a divide-by 32/33 dual modulus prescaler for high speed broadband applications in CMOS 0.18 mum technology. The design uses extended true single phase clock (E-TSPC) logic to decrease the power consumption and enhance the noise performance. The prescaler operates over a wide range of frequencies: 210 MHz to 5.3 GHz. It makes the circuit suitable for multiband multimode operation. The circuit drains only 2.53 mW from a 1.8 V supply voltage. The achieved noise floor is -167 dBc/Hz at 3 GHz" @default.
- W2015184974 created "2016-06-24" @default.
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- W2015184974 date "2005-01-01" @default.
- W2015184974 modified "2023-09-27" @default.
- W2015184974 title "A CMOS broadband divide-by-32/33 dual modulus prescaler for high speed wireless applications" @default.
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- W2015184974 doi "https://doi.org/10.1109/mwscas.2005.1594069" @default.
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