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- W2015262937 abstract "In this paper we address the problem of modeling the timing behavior of a new class of reconfigurable logic gates based on electrostatically controlled graphene pn-junctions. These gates naturally behave as a 2-to-1 multiplexer in which the polarity of the input select line can be dynamically reconfigured. Interconnection of multiple gates and proper assignments of the inputs signals allow to implement all the basic Boolean logic functions, and, at a larger scale, any digital circuit." @default.
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- W2015262937 date "2013-05-02" @default.
- W2015262937 modified "2023-09-23" @default.
- W2015262937 title "Delay model for reconfigurable logic gates based on graphene PN-junctions" @default.
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- W2015262937 doi "https://doi.org/10.1145/2483028.2483099" @default.
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