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• W2015286265 abstract "A large increase of the number of devices integrated in a single chip in conjunction with the significant demands of modern applications for performance has led the designers to a system development methodology based on integrating multiple pre-verified intellectual property cores . Yet, design productivity requirements push designers to focus on key micro-architectural solutions to manage more efficiently the scaling of multi-core SoCs as well as to increase the degree of design automation, particularly as rapid prototyping using reconfigurable computing is becoming mainstream. In this paper we present a novel interconnect architecture based on optimized components to efficiently manage SoCs that follow either a multi-core based approach or are built to support SIMD-style applications that can exploit the processing power of a pool of hardware resources; first we analyze the design of a crossbar featuring shared-memory combined input-crosspoint buffering as a solution for efficient implementation of on-chip interconnection; second we describe the design of a load-balancer featuring configurable proportional allocation of on-chip resources and in-order delivery as a solution for efficient scheduling and execution of processing tasks. The main focus of the paper is to describe and evaluate the mechanisms designed to distribute and manage data transfers so as to implement an efficient interconnection of the integrated cores and control access to available (either on-chip or off-chip) resources for the implementation of a number of embedded systems and applications . Each of these challenges is handled by the proposed architecture in an efficient way in terms of performance, cost in silicon and flexibility." @default.
• W2015286265 created "2016-06-24" @default.
• W2015286265 creator A5001630802 @default.
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• W2015286265 date "2010-11-01" @default.
• W2015286265 modified "2023-09-24" @default.
• W2015286265 title "Design and implementation of high-speed buffered crossbars with efficient load balancing for multi-core SoCs" @default.
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• W2015286265 doi "https://doi.org/10.1016/j.micpro.2010.06.002" @default.
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