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• W2015428081 abstract "As CMOS scaling extends into the nanoscale regime, designers need to be aware that device behavior depends not only on traditional geometric parameters such as channel length and width, but also on layout implementation details of the device and its surrounding neighborhood. The advent of stress engineering, in which intentional mechanical stress is applied to improve device performance, also adds new geometric dependencies. This paper reviews the major process technology features that cause layout-dependent proximity effects and how to account for these effects in circuit and layout design." @default.
• W2015428081 created "2016-06-24" @default.
• W2015428081 creator A5071648602 @default.
• W2015428081 date "2010-09-01" @default.
• W2015428081 modified "2023-10-05" @default.
• W2015428081 title "Layout-dependent proximity effects in deep nanoscale CMOS" @default.
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• W2015428081 doi "https://doi.org/10.1109/cicc.2010.5617407" @default.
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