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- W2015821239 abstract "A 19-27 Gbps receiver comprised of a continuous-time linear equalizer (CTLE) followed by a 2-tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the advantages of small form factor and wide range operation (19-27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> only." @default.
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- W2015821239 date "2015-11-01" @default.
- W2015821239 modified "2023-10-10" @default.
- W2015821239 title "A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery" @default.
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- W2015821239 doi "https://doi.org/10.1109/jssc.2015.2475122" @default.
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