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• W2015936334 endingPage "046502" @default.
• W2015936334 startingPage "046502" @default.
• W2015936334 abstract "We investigated a device isolation process for MoS2-based devices and fabricated high-k/metal-gate MoS2 MOSFETs. An Ar-ion etching process was utilized for the device isolation process. It circumvents damage in the device channel, as confirmed by Raman spectroscopy. A top-gate MoS2 MOSFET was fabricated with a HfO2 thin film 16 nm thick as the gate insulator. Utilizing capacitance–voltage (C–V) measurements, the capacitance equivalent thickness (CET) was estimated to be 5.36 nm, which indicates that a gate stack with the sufficiently thin insulator was successfully realized. The device exhibited a mobility of 25.3 cm2/(V·s), a subthreshold swing (SS) of 86.0 mV/decade, and an ON/OFF ratio of 107. This satisfactory device performance demonstrates the feasibility of the proposed device isolation process." @default.
• W2015936334 created "2016-06-24" @default.
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• W2015936334 date "2015-03-20" @default.
• W2015936334 modified "2023-10-18" @default.
• W2015936334 title "Fabrication of high-<i>k</i>/metal-gate MoS₂field-effect transistor by device isolation process utilizing Ar-plasma etching" @default.
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• W2015936334 doi "https://doi.org/10.7567/jjap.54.046502" @default.
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