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• W2016046069 abstract "Double-edged pulsewidth modulation (DPWM) is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. This paper presents an 8-/9-bit line-coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buffering required in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for high-speed data recovery. The DPWM transceiver is implemented in a 45-nm CMOS Silicon on insulator and operates at 10 Gbit/s with $10^{-12}$ bit error rate and consumes 96 mW. The power consumption of the 8-/9-bit coding hardware is 1.5 mW at 10 Gbit/s demonstrating low-power overhead." @default.
• W2016046069 created "2016-06-24" @default.
• W2016046069 creator A5024558404 @default.
• W2016046069 creator A5046597133 @default.
• W2016046069 date "2016-02-01" @default.
• W2016046069 modified "2023-09-24" @default.
• W2016046069 title "Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication" @default.
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• W2016046069 doi "https://doi.org/10.1109/tvlsi.2015.2409297" @default.
• W2016046069 hasPublicationYear "2016" @default.
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