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- W2016047029 abstract "Abstract Latch-up triggered by an impulse of short duration, is one root cause for field failures of CMOS devices. Standard tests, like JEDEC 78, which apply quasi-static overvoltage and overcurrent may fail to identify this susceptibility. The presented test method and setup allows to study the transient induced latch-up (TLU) phenomenon employing nstrigger impulses at wafer-level and package-level. A TLU-module superimposes the DC voltage of the power supply with a short stress pulse and delivers the combination to the tested pin of the DUT, avoiding destructive EOS. Closest possible distances between the TLU-module and the DUT and the use of RF-probes at wafer level allow risetimes of less than 1 ns, time resolved measurements of voltage and current, and an almost instantaneous limitation of the supply current after latch-up has been triggered. The short stress pulses were generated by transmission lines or solid state pulse generators. Abrupt changes in the voltage and current amplitudes indicate that latch-up has been triggered. The method is successfully demonstrated for several devices in different technologies." @default.
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- W2016047029 date "2006-09-01" @default.
- W2016047029 modified "2023-09-25" @default.
- W2016047029 title "Transient-induced latch-up test setup for wafer-level and package-level" @default.
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- W2016047029 doi "https://doi.org/10.1016/j.microrel.2006.08.002" @default.
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