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- W2016222123 abstract "The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set–Reset (S–R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW." @default.
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- W2016222123 date "2011-05-01" @default.
- W2016222123 modified "2023-10-16" @default.
- W2016222123 title "Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage" @default.
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- W2016222123 doi "https://doi.org/10.1016/j.mejo.2011.01.006" @default.
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