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- W2016319943 abstract "The aim of the present work is to study the evolution of Si based heterostructure MOSFETs via the incorporation of new materials, for example strained-Si, and to predict the resultant device performance and scaling trends of strained-Si/SiGe MOSFETs for RF applications. The article describes a comprehensive technology CAD (TCAD) based methodology to design and optimize strained-Si channel of CMOS technology using Sentaurus tools. Sentaurus-PROCESS is used to simulate and optimize a typical 90/45-nm process flow, including channel, halo, source/drain (S/D) profile engineering, oxidation, deposition, etching, and annealing for dopant activation. The structure generated by Sentaurus-PROCESS is then simulated using the device simulator Sentaurus-DEVICE. The simulation results have been benchmarked with reported experimental strained-Si channel MOSFET device results. The calibrated n- and p-type devices are scaled down to a 45 nm gate length to assess the device and circuit behavior." @default.
- W2016319943 created "2016-06-24" @default.
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- W2016319943 date "2007-05-01" @default.
- W2016319943 modified "2023-10-16" @default.
- W2016319943 title "Scaling of Strain-Engineered MOSFETs" @default.
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- W2016319943 doi "https://doi.org/10.1080/03772063.2007.10876140" @default.
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