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- W2016376185 abstract "In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20% can be achieved. Simulation results from NORA designs in a 0.18-mum CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction" @default.
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- W2016376185 date "2006-12-01" @default.
- W2016376185 modified "2023-09-27" @default.
- W2016376185 title "A Design Technique for Energy Reduction in NORA CMOS Logic" @default.
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- W2016376185 doi "https://doi.org/10.1109/tcsi.2006.885690" @default.
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