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• W2016570462 abstract "This paper deals with the problem of mapping a computation-intensive task of irregular structure onto a parallel framework. Our application is the switch-level logic simulation of digital circuits, a technique that is in wide use for the verification of VLSI designs. We focus on medium-grain multiprocessors (shared memory or message passing machines) and only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. We address the issues of portability and scalability and look at specific features of the application that can be exploited. Different ways of mapping the simulation problem onto a parallel framework are presented. A prototype implementation of our algorithms is described. Experimental results demonstrate the potential for speedup and highlight the problem of close coupling between processors due to distributed iteration." @default.
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• W2016570462 date "1990-10-01" @default.
• W2016570462 modified "2023-09-23" @default.
• W2016570462 title "Design of a scalable parallel switch-level simulator for VLSI" @default.
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• W2016570462 doi "https://doi.org/10.5555/110382.110592" @default.
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