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- W2017310273 abstract "As the density, complexity, and speed of VLSI circuits are continuing to increase, the management of on-chip interconnects becomes of paramount concern to the I.C. designer, especially with respect to internal noise immunity. This paper presents two methods for analyzing and predicting the line-to-line coupling between high-speed VLSI interconnects using distributional and lumped element analysis techniques. In a broader sense, the analyses presented provide all pertinent line capacitances and inductances needed to characterize any array of interconnect. The basic model consists of representing the interconnects as a regular periodic array, considering the worst-case interaction occurring between two adjacent lines. It is shown that the proximity of a ground plane is essential in achieving acceptable (> 20 db) isolation between interconnects that are used specifically for reasonably long data and control distribution functions. This translates to the eventual establishment of scaling rules for linewidth and spacing with respect to field oxide thickness." @default.
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- W2017310273 date "1984-08-01" @default.
- W2017310273 modified "2023-10-18" @default.
- W2017310273 title "An analysis of interconnect line capacitance and coupling for VLSI circuits" @default.
- W2017310273 doi "https://doi.org/10.1016/0038-1101(84)90022-4" @default.
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