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- W2017346811 abstract "Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naive way-reduction scheme (that simply discards faulty cache lines), respectively." @default.
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- W2017346811 date "2012-06-03" @default.
- W2017346811 modified "2023-09-24" @default.
- W2017346811 title "Exploiting narrow-width values for process variation-tolerant 3-D microprocessors" @default.
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- W2017346811 doi "https://doi.org/10.1145/2228360.2228581" @default.
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