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- W2017361567 abstract "Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance distributions at a late stage (e.g., post-layout simulation). BMF statistically models the correlation between early-stage and late-stage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown late-stage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75× runtime speedup over the traditional kernel estimation method." @default.
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- W2017361567 date "2012-11-05" @default.
- W2017361567 modified "2023-10-18" @default.
- W2017361567 title "Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion" @default.
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- W2017361567 doi "https://doi.org/10.1145/2429384.2429519" @default.
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