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- W2017479249 abstract "We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rent's rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device (PLD) [or field-programmable gate array (FPGA)] and a useful measure of its routing flexibility. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound." @default.
- W2017479249 created "2016-06-24" @default.
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- W2017479249 date "2007-08-01" @default.
- W2017479249 modified "2023-10-18" @default.
- W2017479249 title "Post-Placement Interconnect Entropy" @default.
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- W2017479249 doi "https://doi.org/10.1109/tvlsi.2007.900747" @default.
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