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• W2017503457 abstract "The TILE64 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>TM</sup> processor is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. A figure shows a block diagram with 64 tile processors arranged in an 8x8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux." @default.
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• W2017503457 date "2008-02-01" @default.
• W2017503457 modified "2023-10-16" @default.
• W2017503457 title "TILE64 - Processor: A 64-Core SoC with Mesh Interconnect" @default.
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• W2017503457 doi "https://doi.org/10.1109/isscc.2008.4523070" @default.
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