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- W2017695087 abstract "As advances in manufacture technology, leakage current increases dramatically in modern ICs. By turning off supply voltage in a low-power domain with power switches, power gating becomes a useful technique in resolving this problem. Since number and locations of power switches have great impact on chip area and IR-drop, an efficient and effective approach to insert power switches is required for the power gating designs. Unlike previous works using the greedy algorithm to handle this problem, this paper uses a simplified model to approximate required equivalent resistance of power switches in a low-power domain, and then determines number and types of power switches based on the value. In order to reduce impact on preplaced standard cells, we also propose a mathematical approach to find locations with less placement density to place power switches. The proposed methodology was integrated into a real-design flow. Experimental results demonstrate that our approach can insert less number of power switches and still satisfy the IR-drop constraint than other approaches." @default.
- W2017695087 created "2016-06-24" @default.
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- W2017695087 date "2015-05-01" @default.
- W2017695087 modified "2023-09-24" @default.
- W2017695087 title "Placement Density Aware Power Switch Planning Methodology for Power Gating Designs" @default.
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- W2017695087 doi "https://doi.org/10.1109/tcad.2015.2401573" @default.
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