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- W2017753529 abstract "This paper analyzes and models the narrow width effect (NWE) observed in nMOS transistors fabricated using a 28-nm gate-first CMOS process. It is shown that the threshold voltage of nMOS transistors increases with decrease in channel width and this effect is enhanced at shorter gate lengths, thicker hafnium oxide (HfO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> ), and thicker lanthanum (La) capping layer. It is also observed that this increase in threshold voltage for narrow width transistors is influenced by the device layout. The physical mechanisms responsible for the observed anomalous behavior are identified through measurements on different test structures. An empirical model is proposed to understand and model this behavior. The accuracy of the model is verified by comparing it with the experimental data. It is finally proposed that the observed NWE could be minimized by optimizing the thickness of HfO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> , La capping layer, and SiO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> interfacial layer and by using different device layouts." @default.
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- W2017753529 date "2015-04-01" @default.
- W2017753529 modified "2023-10-16" @default.
- W2017753529 title "Analysis and Modeling of the Narrow Width Effect in Gate-First HKMG nMOS Transistors" @default.
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- W2017753529 doi "https://doi.org/10.1109/ted.2015.2398870" @default.
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