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- W2017861750 abstract "The authors describe the main topics related to a real-time implementation of the Proposed Federal Standard 1016 (PFS-1016) 4800 bps CELP (code excited linear prediction) voice coder together with some alternatives to extend real-time CELP schemes over a wide range of bit rates (8000, 6500, and 2400 bps are considered). Several procedures are evaluated in order to select the options in PFS-1016 that provide the highest quality for an implementation based on a single AT&T DSP32C chip. From the basic CELP scheme, higher and lower bit rates are derived after evaluation of the efficiency obtained for the different elements in this speech coding algorithm.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2017861750 date "1991-01-01" @default.
- W2017861750 modified "2023-10-16" @default.
- W2017861750 title "Real-time implementation and evaluation of variable rate CELP coders" @default.
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- W2017861750 doi "https://doi.org/10.1109/icassp.1991.150407" @default.
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