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• W2017889564 abstract "Since multicore architectures are becoming more popular, recent multicore optimizations focus on energy consumption. In this paper, we focus on reducing the energy consumption in the data and instruction cache hierarchies in a multicore system. First, we present a level one data cache tuning heuristic for a heterogeneous multicore system, which classifies applications based on data sharing and cache behavior and uses this classification to guide cache tuning and reduce the number of cores that need to be tuned. Results reveal average energy savings of 25 percent for 2, 4, 8, and 16-core systems while searching only 1 percent of the design space. Next, we present a level one instruction cache tuning heuristic that reduces energy consumption in the instruction cache hierarchy by an average of 53 percent for 2, 4, 8, and 16-core systems, while searching less than 1 percent of the design space. Finally, we develop a custom, global hardware cache tuner for a dual-core system and show that our cache tuner has low area, energy, and power overheads." @default.
• W2017889564 created "2016-06-24" @default.
• W2017889564 creator A5035415168 @default.
• W2017889564 creator A5060374059 @default.
• W2017889564 date "2013-08-01" @default.
• W2017889564 modified "2023-10-14" @default.
• W2017889564 title "A Cache Tuning Heuristic for Multicore Architectures" @default.
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• W2017889564 doi "https://doi.org/10.1109/tc.2013.44" @default.
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