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- W2018352709 abstract "Very low gate delays of 7.7 ps at 1 V supply and 4.7 ps at 2 V supply have been achieved for CMOS inverters fabricated on a 90 nm silicon on insulator technology. The results are measured with an optimised CMOS ring oscillator. These are believed to be the lowest gate delays reported to date for CMOS inverters at room temperature." @default.
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- W2018352709 date "2004-01-01" @default.
- W2018352709 modified "2023-09-24" @default.
- W2018352709 title "Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology" @default.
- W2018352709 cites W1491885026 @default.
- W2018352709 doi "https://doi.org/10.1049/el:20046031" @default.
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