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• W2019266502 abstract "3D-IC design facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals. The dynamic power consumption of interconnects in 3D-IC is contributed by wires, buffers and TSVs. The delay in interconnects for 3D-IC is greatly influence by TSV capacitance. In this paper we propose TSV capacitance-aware 3D floorplanning to reduce the delay and dynamic power consumption in 3D-interconnects. The TSVs with specified dimensions and pitch are positioned in islands. TSV islands offer advantages over individual TSVs like reduced stress impact and more efficient inclusion of redundancy. TSV capacitance depends on TSV dimensions, pitch and wire technology. TSV capacitance aware floorplanning reduces power consumption in interconnects on average by 7% when using Cu-TSVs and 9% for W-TSVs. The approach also reduces peak delay for nets using Cu based TSVs on average by 15% and W based TSVs by 21%." @default.
• W2019266502 created "2016-06-24" @default.
• W2019266502 creator A5040622659 @default.
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• W2019266502 date "2013-10-01" @default.
• W2019266502 modified "2023-09-25" @default.
• W2019266502 title "TSV capacitance aware 3-D floorplanning" @default.
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• W2019266502 doi "https://doi.org/10.1109/3dic.2013.6702358" @default.
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