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- W2019334960 abstract "Many practical applications include matrix operations as essential procedures. In addition, recent studies of matrix operations rely on parallel processing to reduce any calculation delays. Because these operations are highly data intensive, many studies have investigated work distribution techniques and data access latency to accelerate algorithms. However, previous studies have not considered hardware architectural features adequately, although they greatly affect the performance of matrix operations. Thus, the present study considers the architectural characteristics that affect the performance of matrix operations on real multicore processors. We use matrix multiplication, LU decomposition, and Cholesky factorization as the test applications, which are well-known data-intensive mathematical algorithms in various fields. We argue that applications only access matrices in a particular direction, and we propose that the canonical data layout is the optimal matrix data layout compared with the block data layout. In addition, the tiling algorithm is utilized to increase the temporal data locality in multilevel caches and to balance the workload as evenly as possible in multicore environments. Our experimental results show that applications using the canonical data layout with tiling have an 8.23% faster execution time and 3.91% of last level cache miss rate compared with applications executed with the block data layout. • We propose the optimal matrix layout for data-intensive parallel matrix operations. • We achieve reduced data latency through the optimized canonical data layout. • Loop transformation using “tiling” is used for efficient parallel algorithms. • The proposed optimized canonical data layout outperforms the existing block data layout." @default.
- W2019334960 created "2016-06-24" @default.
- W2019334960 creator A5015417010 @default.
- W2019334960 creator A5017913155 @default.
- W2019334960 date "2014-07-01" @default.
- W2019334960 modified "2023-09-24" @default.
- W2019334960 title "Architectural investigation of matrix data layout on multicore processors" @default.
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- W2019334960 doi "https://doi.org/10.1016/j.future.2013.10.020" @default.
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