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- W2019398439 abstract "Atomic layer deposited high-k dielectrics with sputtered TiOx as the seeding layer have been explored for double layer graphene tunnel transistors. The subthreshold swing of these transistors is <100 mV/decade. Temperature-dependent measurements indicate defect-mediated tunneling through these dielectrics. However, the current symmetry can still be altered by engineering the tunnel barriers." @default.
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- W2019398439 date "2013-09-01" @default.
- W2019398439 modified "2023-10-17" @default.
- W2019398439 title "Barrier engineering for double layer CVD graphene tunnel FETs" @default.
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